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Features
* * * * *
Digital Self-supervising Watchdog with Hysteresis One 250-mA Output Driver for Relay Enable Output Open Collector 8 mA Over/Undervoltage Detection ENABLE and RELAY Outputs Protected Against Standard Transients and 40 V Load Dump * ESD Protection According to MIL-STD-883 D Test Method 3015.7 - Human Body Model: 2 kV (100 pF, 1.5 kW) - Machine Model: 200 V (200 pF, 0 W)
Special Fail-safe IC U6808B
Description
The U6808B is designed to support the fail-safe function of a safety critical system (e.g., ABS). It includes a relay driver, a watchdog controlled by an external R/C-network and a reset circuit initiated by an over and undervoltage condition of the 5-V supply providing a low-level reset signal. Figure 1. Block Diagram
VS VS Bandgap reference 2.44 V Power-on reset RESET Reset debounce + RELAY Reset delay
+ -
Under/ overvoltage detection
ENABLE RIN + + -
Internal oscillator Watchdog RC oscillator
Current limitation
WDI
GND
WDC
Rev. 4707A-AUTO-05/03
1
Pin Configuration
Figure 2. Pinning SO8
RELAY
1
8
VS
GND
2
7
RIN
ENABLE
3
6
WDI
WDC
4
5
RESET
Pin Description
Pin 1 2 3 4 5 6 7 8 Symbol RELAY GND ENABLE WDC RESET WDI RIN VS Type Open collector driver output Supply Digital output Analog input Digital output Digital input Digital input Supply Function Fail-safe relay driver Standard ground Negative reset signal External RC for watchdog timer Negative reset signal Watchdog trigger signal Activation of relay driver 5-V supply Logic No signal: driver off Low: driver on No signal Low: reset No signal Low: reset Pulse sequence High: driver on Low: driver off -
Fail-safe Functions
A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the pins (e.g., short circuit). This ensures that a microcontroller system is not brought into a critical status. A critical status is reached if the system is not able to switch off the relay and to give a signal to the microcontroller via the ENABLE and RESET outputs. The following table shows the fault conditions for the pins.
Short to Vs Relay on Short to VBat Relay on Short to GND Relay off Open Circuit Relay off
Table 1. Table of Fault Conditions
Pin RIN Function Digital input to activate the fail-safe relay Watchdog trigger input Capacitor and resistor of watchdog Driver of the fail-safe relay
WDI OSC RELAY
Watchdog reset Watchdog reset
Watchdog reset Watchdog reset
Watchdog reset Watchdog reset Relay on
Watchdog reset Watchdog reset Relay off
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Truth Tables
Table 2. Truth Table for Over and Undervoltage Conditions
Supply Voltage (VS) Normal Too low Too high Relay Input (RIN) Low High Low High Low High Relay Output Driver (RELAY) Off On Off Off Off Off RESET Output (RESET) High High Low Low Low Low Enable Output Driver (ENABLE) Off Off On On On On
Table 3. Truth Table for Watchdog Failures (Reset Output Do Not Care)
Watchdog Input (WDI) Normal Too slow Too fast Relay Input (RIN) Low High Low High Low High Relay Output Driver (RELAY) Off On Off Off Off Off Enable Output Driver (ENABLE) Off Off On On On On
Description of the Watchdog
Figure 3. Watchdog Block Diagram
RCOSC
Binary counter
Dual MUX
WDI
Slope detector
Up/down counter
RS-FF
WD-OK
RESET OSCERR
Abstract
The microcontroller is monitored by a digital window watchdog which accepts an incomming trigger signal of a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog's time window is determined by external R/C components. The following description refers to the block diagram, see Figure 3.
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WDI Input
The microcontroller has to provide a trigger signal with the frequency fWDI which is fed to the WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and clocks the up/down counter additionally. The latter one counts only from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches status 3 the RS flip-flop is set (see Figure 4). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see section "WD-OK Output") and resets the up/down counter directly. With an external R/C circuitry the IC generates a time base (frequency fWDC) independent from the microcontroller. The watchdog's time window refers to a frequency of fWDC = 100 fWDI
RCOSC Input
OSCERR Input
A smart watchdog has to ensure that internal problems with its own time base are detected and do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating a signal is fed to the OSCERR input after a timeout delay. It resets the up/down counter and disables the WD-OK output. Without this reset function the watchdog would freeze in its current status when fRC stops.
RESET Input WD-OK Output
During power-on and under/overvoltage detection a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state. After the up/down counter is incremented to status 3 (see Figure 4) the RS flip-flop is set and the WD-OK output becomes logic 1. This information is available for the microcontroller at the open-collector output ENABLE. If on the other hand the up/down counter is decremented to 0 the RS flip-flop is reset, the WD-OK output and the ENABLE output are disabled. The WD-OK output also controls a dual MUX stage which shifts the time window by one clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal good or false. The WD-OK signal is also reset in case the watchdog counter is not reset after 250 clocks (missing trigger signal).
Watchdog State Diagram Figure 4. Watchdog State Diagram
good Initial status bad bad O/F bad good 1/F good bad 2/F good 1/NF bad bad 3/NF 2/NF good good
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Explanation
In each block, the first character represents the state of the counter. The second notation indicates the fault status of the counter. A fault status is indicated by an F and a no fault status is indicated by an NF. When the watchdog is powered up initially, the counter starts out at the 0/F block (initial state). Good indicates that a pulse has been received whose width resides within the timing window. Bad indicates that a pulse has been received whose width is either too short or too long.
Watchdog Window Calculation
Example with Recommended Values RC Oscillator Cosc = 3.3 nF (should be preferably 10%, NPO) Rosc = 39 kW (may be 5%, Rosc < 100 kW due to leakage current and humidity) tWDC(s) = 10-3 [Cosc (nF) [(0.00078 Rosc (kW)) + 0.0005]] fWDC(Hz) = 1/(tWDC) Watchdog WDI fWDI(Hz) =0.01 fWDC tWDC = 100 s (R) fWDC = 10 kHz fWDI = 100 Hz (R) tWDI = 10 ms WDI Pulse Width for Fault Detection after 3 Pulses Upper watchdog window Minimum: 169/fWDC = 16.9 ms (R) fWDC/169 = 59.1 Hz Maximum: 170/fWDC = 17.0 ms (R) fWDC/170 = 58.8 Hz Lower watchdog window Minimum: 79/fWDC = 7.9 ms (R) fWDC/79 = 126.6 Hz Maximum: 80/fWDC = 8.0 ms (R) fWDC/80 = 125.0 Hz WDI Dropouts for Immediate Fault Detection Minimum: Maximum: 250/fWDC = 25 ms 251/fWDC = 25.1 ms
Figure 5. Watchdog Timing Diagram with Tolerances
Time/s 79/fWDC 80/fWDC 169/fWDC 170/fWDC 250/fWDC 251/fWDC
Watchdog window update rate is good Update rate is too Update rate is fast either too fast or good Update rate is Update rate is too Update rate is Pulse has either too slow or slow either too slow or dropped out good pulse has dropped out
Reset Delay
The duration of the over or undervoltage pulses determines the enable and reset output. A pulse duration shorter than the debounce time has no effect on the outputs. A pulse longer than the debounce time results in the first reset delay. If a pulse appears during this delay, a second delay time is triggered. Therefore, the total reset delay time can be longer than specified in the data sheet.
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Absolute Maximum Ratings
Parameters Supply-voltage range Power dissipation VS = 5 V, Tamb = -40C VS = 5 V, Tamb = +125C Thermal resistance Junction temperature Ambient temperature range Storage temperature range Symbol VS Ptot Ptot Rthja Tj Tamb Tstg Value -0.2 to +16 250 150 160 150 -40 to +125 -55 to +155 Unit V mW mW K/W C C C
Electrical Characteristics
VS = 5 V, Tamb = -40 to +125C, reference pin is GND, fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz 10%, fWDI = 100 Hz
Parameters Supply Voltage Operation range general Operation range reset Supply Current Relay off Relay on Digital Input WDI Detection low Detection high Resistance to VS Input current low Input current high Zener clamping voltage Digital Input RIN Detection low Detection high Resistance to GND Input current low Input current high Zener clamping voltage Digital Output RESET with Internal Pull-up Voltage high Voltage low Zener clamping voltage Reset debounce time Switch to low Pull-up = 6 kW I 1 mA 1.2 V < VS < 16 V VZRESET tdeb 0.7 VS + 0.1 0 26 120 320 VS 0.3 30 500 V Input voltage = 0 V Input voltage = VS VZRIN -0.2 0.7 VS 10 -5 100 20 0.2 VS VS + 0.5 V 40 +5 550 24 V V kW A A V Input voltage = 0 V Input voltage = VS VZWDI -0.2 0.7 VS 10 100 -5 20 0.2 VS VS + 0.5 V 40 550 +5 24 V V kW A A V Tamb = - 40C Tamb = +125C Tamb = - 40C Tamb = +125C 6 15 mA mA mA mA VS VS 4.5 1.2 5.5 16.0 V V Test Conditions Symbol Min. Typ. Max. Unit
V V s
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Electrical Characteristics (Continued)
VS = 5 V, Tamb = -40 to +125C, reference pin is GND, fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz 10%, fWDI = 100 Hz
Parameters Reset delay time Saturation voltage low Zener clamping voltage Current limitation Leakage current Reset debounce time Reset delay time Relay Driver Output RELAY Saturation voltage Maximum load current Zener clamping voltage Turn-off enegy Leakage current Reset and VS Control Lower reset level Upper reset level Hysteresis Reset debounce time Reset delay RC Oscillator WDC Oscillator frequency Watchdog Timing Power-on-reset prolongation time Detection time for RC oscillator fault Time interval for over-/undervoltage detection Reaction time of RESET output over/undervoltage Nominal frequency for WDI Nominal frequency for WDC Minimum pulse duration for a securely WDI input pulse detection Frequency range for a correct WDI signal fRC = 100 fWDI fWDI = 1/100 fWDC VRC = const. tPOR tRCerror tD,OUV tR,OUV fWDI fWDC tP,WDI fWDI 34 .3 81.9 0.16 0.187 10 1 182 64.7 112.5 103.1 246 0.64 0.72 130 13 ms ms ms ms Hz kHz s Hz ROSC = 39 kW, COSC = 3.3 nF fWDC 9 10 11 kHz VS VS 4.5 5.35 25 120 20 320 50 4.7 5.6 100 500 80 V V mV s ms VR = 16 V VR = 26 V IR16 IR26 I 250 mA I 130 mA Tamb = -40 to +90C Tamb > 90C VRsat VRsat IR IR VZR 250 200 26 30 20 200 30 0.5 0.3 V V mA mA V mJ A A VEN = 5 V VEN = 16 V VEN = 26 V Switch to low Switch back to high Test Conditions Switch back to high I 8 mA VZEN Ilim IEN5 IEN16 IEN26 tdeb tdel 120 320 85 Symbol tdel 0.01 26 8 20 100 200 500 Min. Typ. 50 0.5 30 Max. Unit ms V V mA A A A s ms
Digital Output ENABLE with Open Collector
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Electrical Characteristics (Continued)
VS = 5 V, Tamb = -40 to +125C, reference pin is GND, fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz 10%, fWDI = 100 Hz
Parameters Number of incorrect WDI trigger counts for locking the outputs Number of correct WDI trigger counts for releasing the outputs Detection time for a stucked WDI signal Watchdog Timing Relative to fWDC Minimum pulse duration for a securely WDI input pulse detection Frequency range for a correct WDI signal Hysteresis range at the WDI ok margins Detection time for a dropped out WDI signal VWDI = const. 250 80 1 251 2 169 Cycles Cycles Cycle Cycles VWDI = const. Test Conditions Symbol nlock nrelease tWDIerror 24.5 Min. Typ. 3 3 25.5 ms Max. Unit
Protection against Transient Voltages According to ISO TR 7637-3 Level 4 (Except Pulse 5)
Pulse 1 2 3a 3b 5 Note: Voltage -110 V +110 V -160 V +150 V 40 V Source Resistance(1) 10 10 50 50 2 Rise Time 100 V/s 100 V/s 30 V/ns 20 V/ns 10 V/ms Duration 2 ms 0.05 ms 0.1 s 0.1 s 250 ms Amount 15.000 15.000 1h 1h 20
1. Relay driver: relay coil with Rmin = 70 W to be added
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Timing Diagrams
Figure 6. Watchdog in Too-fast Condition
Normal operation 5V WDI 0V V Batt RELAY 0V 5V ENABLE 0V Don't care WDI too fast Normal operation
Figure 7. Watchdog in Too-slow Condition
Normal operation 5V WDI 0V V Batt RELAY 0V 5V ENABLE 0V Don't care WDI too slow Normal operation
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Figure 8. Overvoltage Condition
Overvoltage condition > 120 ms > 5.6 V 5V VS 0V V Batt RELAY 0V 5V ENABLE 0V 5V RESET 0V Reset debounce time 1 Reset delay 2nd Reset delay
st
< 120 ms > 5.6 V
3 good WDI pulses
Don't care
Figure 9. Undervoltage Condition
Undervoltage condition > 120 ms 5V VS 0V V Batt RELAY 0V 5V ENABLE 0V 5V RESET 0V Reset debounce time 1st Reset delay 2nd Reset delay 3 good WDI pulses Don't care < 4.5 V < 4.5 V < 120 ms
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Figure 10. Application Circuit
VS = 5 V mC
100 Hz mC
mC
8 0.01 mF
7
6
5
U6808B
1 Relay mC V Batt 2 3 4 Cosc 3.3 nF
Rosc 39 kW
Ordering Information
Extended Type Number Package Remarks
U6808B
SO8
-
Package Information
Package SO8
Dimensions in mm
5.00 4.85 1.4 0.4 1.27 3.81 8 5 0.25 0.10 0.2 3.8 6.15 5.85 5.2 4.8 3.7
technical drawings according to DIN specifications
1
4
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4707A-AUTO-05/03 xM

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